1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device which amplifies a signal read from a memory cell and outputs the same from an output buffer.
2. Description of the Related Art
FIG. 29 is a circuit diagram showing a data read circuit in a conventional semiconductor memory device. The data read circuit includes a control signal generating circuits 930 and 935, a memory cell array portion 200, a row decoder 901, a column decoder 900, an I/O line pair IO and ZIO, a differential amplifier 910, a selector circuit 915, a data latch circuit 920, a read data bus driver circuit 925, a read data bus ZRBUS, inverters 1001 and 1002, an output buffer 47 and an external output terminal DOUT.
Control signal generating circuit 935 includes an address buffer 936, an address change detecting circuit 937, an S-R flip-flop 938, a delay circuit 939, inverters 702 and 704, a NAND gate 703, a delay circuit 940 and an S-R flip-flop 941.
Control signal generating circuit 930 includes a delay circuit 945, NOR gate 710, NAND gates 705 and 706, and inverters 707, 708, 709 and 710.
Memory cell array part 200 includes word lines WL, bit line pairs BL and ZBL, memory cells 711, sense amplifiers 902, and NMOS transistors 720 and 721. Each memory cell 711 includes a memory cell capacitor 903 and a memory cell transistor 710.
Selector circuit 915 includes a PMOS transistor 712, an NMOS transistor 713 and an inverter 714. The selector circuit 915 forms a CMOS transfer gate. Data latch circuit 920 includes inverters 715 and 717 as well as a clocked inverter 716. Read data bus driver circuit 925 includes inverters 718 and 719. Read data bus ZRBUS extends between memory cell array portion 200 and output buffer 47.
Control signal generating circuit 935 receives on its address buffer 936 an external address signal Add. Control signal generating circuit 935 generates the following signals based on the external address signal Add. Address change detecting circuit 937 generates a signal .phi.0. S-R flip-flop 938 generates a signal .phi.1. NAND gate 703 generates a signal .phi.2. S-R flip-flop 941 generates a signal .phi.3.
Control signal generating circuit 930 receives signals as follows. Delay circuit 945 receives an external column address signal Ext.ZCAS. Inverter 708 receives an external output enable signal Ext.ZOE. Inverter 707 receives a signal .phi.3. Control signal generating circuit 930 generates a signal .phi.5 from inverter 710 based on the received signals.
Row decoder 901 selects word line WL. Column decoder 900 receives signal .phi.1 and selects a column select line CSL. Differential amplifier 910 amplifies a potential difference of I/O line pair IO and ZIO to generate a resultant output signal RD.
In selector circuit 915, transistor 712 receives signal .phi.2, and transistor 713 receives signal .phi.2 inverted by inverter 714. Selector circuit 915 applies signal RD to data latch circuit 920 in response to signal .phi.2.
In data latch circuit 920, inverter 715 receives output signals from selector circuit 915 and clocked inverter 716 to generate a signal ZRDA. In data latch circuit 920, clocked inverter 716 receives signal .phi.2 and an inverted signal of the same, and latches signal ZRDA in response to the received signals.
Read data bus driver circuit 925 is responsive to signal ZRDA to drive read data bus ZRBUS. Inverters 1001 and 1002 generate signals OD and ZOD in accordance with the data on read data bus ZRBUS, respectively. Output buffer 47 receives signals .phi.5, OD and ZOD, and outputs external output data signal DOUT from external output terminal DOUT in response to the received signals.
Now, the operation of the read circuit in FIG. 29 will be described below. FIG. 30 is a timing chart showing the operation of the read circuit in FIG. 29.
Description will be given on the case where external signals Ext.ZCAS and Ext.ZOE change their levels from high to low, so that data Y1 in external address signal Add is accessed.
Owing to change of data in external address signal Add from Y0 to Y1, a pulse generates at time t0 in signal .phi.0 supplied from address change detecting circuit 937. At this time, S-R flip-flop 938 is set, so that signal .phi.1 becomes high.
As a result, column decoder 900 selects column select line CSL. Thereby, data read from memory cell 711 is transmitted to I/O line pair IO and ZIO via bit line pair BL and ZBL. Therefore, a potential difference generates between I/O lines IO and ZIO.
Then, upon reception of signal .phi.0, signal .phi.2 becomes low at time t1. Thereby, differential amplifier 910 is activated, and selector circuit 915 becomes conductive. Owing to the fact that selector circuit 915 becomes conductive, data latch circuit 920 outputs signal ZRDA in response to signal RD supplied from differential amplifier 910.
In response to signal ZRDA, read data bus driver circuit 925 drives read data bus ZRBUS. In response to data on read data bus ZRBUS thus driven, inverters 1001 and 1002 generate signals OD and ZOD at time t2, respectively. These signals OD and ZOD are transmitted to output buffer 47. In output buffer 47, signal .phi.5 becomes high at time t3 after transmission of signals OD and ZOD, and at the same time, output buffer 47 starts its operation for supplying external output data signal DOUT.
It is assumed that signal .phi.5 which activates output buffer 47 becomes high at time t30 preceding time t2. In this case, output buffer 47 starts its operation before time t2 at which data read from memory cell 711 is transmitted to output buffer 47. Therefore, output buffer 47 once outputs the high level of signal RD, which is supplied during a standby state of differential amplifier 910, as data read from memory cell 711.
In the aforementioned case, invalid data (high level) opposite to true data (low level) is once output as external output data signal DOUT. Therefore, such a disadvantage generates that the time at which external output signal DOUT became the true data (low level) is delayed by .DELTA.t from the time during the normal operation. In order to overcome the above disadvantage, timing at which output buffer 47 starts its operation must be delayed until the signal sent from differential amplifier 910 reaches output buffer 47.
In a memory of a large capacity, however, a long signal transmission time of read data bus ZRBUS increases in accordance with increase of sizes of a chip, so that a long time is required until the output signal of differential amplifier 910 reaches output buffer 47. Therefore, the timing at which output buffer 47 is activated must be determined taking the variation of performance of transistors, which are interposed between differential amplifier 910 and output buffer 47, into consideration, and by this reason, the timing at which signal .phi.5 becomes high must be delayed further.
However, if the signal .phi.5 does not become high, external output data signal DOUT is not output even if the output signal of differential amplifier 910 reaches output buffer 47. Therefore, if the timing at which signal .phi.5 becomes high is delayed excessively, the access is also delayed excessively, although the invalid data is not output.
As described above, the read circuit in the conventional semiconductor memory device requires a sufficient margin in connection with the timing of operation of the output buffer in order to prevent output of invalid data during the data read operation. This restricts the speed of the address access operation.
Further, the operation timing of the output buffer is determined by the delay circuit included in the control signal generating circuit, so that it is impossible to output the external output signal at the same timing as the reading of data onto the data bus during the address access operation, resulting in a low speed of the data read operation.